Method for the generation of pulse-width-modulated signals and associated signal generator

ABSTRACT

A pulse-width-modulated signal is generated out of a sampled reference signal. The least significant bits of a sample of the reference signal are stored in a comparison register. At the same time, a check is made in a test circuit to find out if the sample considered corresponds to a maximum amplitude of the reference signal. If this is the case, an overflow bit is given. The overflow bit and the least significant bits of the sample considered are then linked together to obtain a comparison word. The comparison word is compared with a number given by the counter to generate the pulse-width-modulated signal.

FIELD OF THE INVENTION

[0001] The present invention relates to pulse-width-modulated (PWM)signals.

BACKGROUND OF THE INVENTION

[0002] Pulse-width-modulated signals are useful, for example, for thecontrol of asynchronous motors or inverters used in householdappliances, ventilation air control systems, pumping systems and thelike. A pulse-width-modulated signal SC (FIG. 1c) is a cyclical signalthat is activated periodically (A_(i), A_(i+1)), and deactivated atvariable points in time (D_(i), D_(i+1)) between two operations ofactivation. The time TC between two operations of activation is called aswitching period. The ratio TC1/TC between the duration of the activesignal and the switching period is called a cyclical ratio. The signalSC may be active at 0 or at 1.

[0003] When a pulse-width-modulated signal is used to control anasynchronous motor, the variations in time of the cyclical ratio of thecontrol signal lead to similar variations in current in the phase orphases of the motor. For example, with an appropriate control signal SC,sinusoidal variations of the current can be obtained in the phase orphases of the motor.

[0004] A pulse-width-modulated signal SC is conventionally obtained by agenerator that produces the signal SC from a reference signal SREF whichis a sampled analog signal. The initial analog signal may have a sine(FIG. 1a), trapezoidal, square or any other shape. The sample referencesignal SREF (FIG. 1b) is obtained by the sampling of the initial analogsignal. It comprises a set of binary numbers E₀ to E_(NBECH) whose valuedepends on the amplitude of the signal at the instant considered. Thesmallest value of the numbers E₀ to E_(NBECH), for example, equal to 0,is associated with the sample having the smallest amplitude. Conversely,the highest value of the numbers E₀ to E_(NBECH) is associated with thegreatest amplitude of the initial signal.

[0005] The number of signals chosen NBECH is a compromise between thedesired precision (which increases with the number of samples) and thecomputation time needed to obtain the signal SC from the sampledreference signal SREF (which also increases with the number of samples).For example, in the case of an initial sine analog signal, it could bechosen to take 360 samples, i.e., every 1⁰ on a period TREF=360° of theanalog signal, or else 2^(N) samples every TREF/2^(N) on a period TREFof the analog signal, with N being the size of a register of thecircuit.

[0006] A known generator of pulse-width-modulated signals is shown inFIG. 2. The generator has a counter CPC, a reference memory MR, acomparison register RC and a comparator CPT. The numbers E₀ to E_(NBECH)are stored in the reference memory MR of the generator. The M-bitcounter CPC counts pulses of a clock signal CP and gives a number ofcounted pulses NB varying between 0 and NBMAX=2^(M)−1. When the numberNBMAX is reached, the counter returns to zero and then starts countingagain.

[0007] The samples E₀ to E_(NBCH) of the sampled reference signal SREFcontained in the reference memory MR are successively loaded into thecomparison register RC. A sample E_(i) is loaded at each return to zeroof the counter CPC. As the case may be, the same sample E_(i) may beloaded several times successively. In every case, a loading is done ateach return of the counter to zero.

[0008] The comparator CPT continuously compares the number NB given bythe counter with the sample E_(i) contained in the comparison registerRC. The comparator CPT gives the control signal SC having the followingproperties. For every value of i ranging from 0 to NBECH, SC is activewhen NB<E_(i), and SC is inactive when NB≧E_(i).

[0009]FIG. 1c shows the development of the number NB, the samples E_(i)and the signal SC resulting in one example. The signal SC is active at 1and inactive at 0. The signal SC is thus activated at each return tozero of the counter, and then deactivated when the number NB given bythe counter exceeds the value E_(i) of the sample contained in thecomparison register RC.

[0010] Referring to FIG. 1C, a pulse signal is obtained. In this signal,the width of the active pulses (and hence the cyclical ratio) varies intime as a function of the value E_(i) of the samples of the referencesignal SREF, and hence as a function of the initial analog signal. Theprecision of the generator depends on the range of variation of thecyclical ratio and on the minimum variation of the cyclical ratio.

[0011] The cyclical ratio R of the control signal SC can be computed asfollows. For each period TC of the counter (since the signal SC isactivated at each return to 0 of the counter): $\begin{matrix}{R = {\left( {E_{i}^{*}{TCP}} \right)/({TC})}} \\{= {\left( {E_{i}^{*}{TCP}} \right)/\left( {\left( {{NBMAX} + 1} \right)^{*}{TCP}} \right)}} \\{= {E_{i}/{\left( {{NBMAX} + 1} \right).}}}\end{matrix}$

[0012] NBMAX=2^(M)−1 is the maximum value of the number NB, M is thesize of the counter, and TCP is the period of the clock signal CP.

[0013] The minimum variation in the cyclical ratio is equal toΔRmin=1/(NBMAX+1). The precision of the generator is directlyproportional to the number NBMAX, namely the size of the counter. Theprecision of the generator increases also with the range of variation ofthe cyclical ratio. It is preferable to have available a generatorproducing control signals whose cyclical ratio varies from 0 to 100% tohave as wide a range of control as possible. In this way, unnecessarylosses and deterioration are avoided in the electronic control circuitsof the motor.

[0014] The minimum value Rmin of the cyclical ration is equal to 0%.This corresponds to E_(i)=0.

[0015] The maximum value of the cyclical ratio is equal to:

Rmax=X/(NBMAX+1).

[0016] X is the maximum value of the numbers E₀ to E_(NBCH). Rmax canreach 100% only if X can reach the value NBMAX+1=2^(M), with M being thesize of the counter. To attain a cyclical ratio of 100%, the numbers E₀to E_(NBCH) should be encoded on a number of bits at least equal to M+1to be able to reach the value 2^(M).

[0017] If the register RC used has a size N (for example, N=16) greaterthan the size M (for example, M=12) of the counter CPC, this does notraise any problems. It is possible to use 13-bit numbers E_(i) which areloaded into the register RC and then are compared with the 12-bitnumbers NB given by the counter. It is also possible to use 16-bitnumbers E_(i) (enabling higher precision to be obtained on the sampledsignal). These numbers are loaded into the register RC, and only the 13most significant bits of the numbers E_(i) are compared with the 12-bitnumbers NB given by the counter CPC.

[0018] A problem arises, however, when the registers and the counterhave an identical size. A first known approach uses two comparisonregisters, the first to store the N least significant bits of thenumbers E₀ to E_(NBCH), and the second to store the most significantbits of these numbers. This approach, however, is not worthwhile becauseit implies the loading of two registers at each return of the counter tozero. This increases the time for loading the numbers E_(i), andtherefore the time for computing the signal SC. Furthermore, the size ofthe circuit is increased.

[0019] In a second approach, only the M-1 least significant bits of thecounter CPC are used to produce the M-1 bit numbers NB, and the registerRC sized N=M is used to store the numbers E₀ to E_(NBCH). It is thuspossible to attain a cyclical ratio Rmax equal to 100%. This approach,however, is not worthwhile because it impairs the performance of thegenerator by reducing its precision (the number ΔRmin increases).

[0020] Thus, if the registers and the counter of the generator areidentical in size, it is not possible, with the prior art approaches, toobtain an optimum generator that has both maximum precision and minimumcomputation time.

SUMMARY OF THE INVENTION

[0021] In view of the foregoing background, an object of the presentinvention to provide an optimized generator making the most efficientuse of the capacities of its components while at the same timemaintaining high precision and limited computation time.

[0022] This and other objects, advantages and features according to thepresent invention are provided by a method for the generation of apulse-width-modulated signal out of a sampled reference signal, a methodin which a counter is incremented to produce numbers NB incremented ateach pulse of a clock signal. A reference number is updated each timethe counter reaches a setting value. The reference number relates to thereference signal.

[0023] According to the method of the invention, the following steps arealso performed. An overflow bit is computed by comparing a pointer valuewith a reference parameter. The pointer value is updated each time thecounter reaches the setting value. The control signal is produced bycomparing a number NB given by the counter with an updated comparisonword comprising the overflow bit in terms of the most significant bits,and the updated reference number in terms of the least significant bits.

[0024] The invention also relates to an associated generator ofpulse-width-modulated signals. The generator comprises a counter tocount the pulses of the clock signal and provide the numbers NB. Acomparison register stores the reference number.

[0025] According to the invention, the generator also comprises a testcircuit to compute the overflow bit, and an overflow register to storethe overflow bit. A comparator gives the control signal by comparing thenumber NB given by the counter with the updated comparison wordcomprising the overflow bit in terms of most significant bits and theupdated reference number in terms of least significant bits.

[0026] The numbers NB given by the counter and the updated referencenumber are of the same size N. The updated comparison word is a sampleof the reference signal associated with the value of the updatedpointer. The pointer indicates the sampling times. The updated referencenumber is obtained by eliminating the most significant bit of the sampleof the reference signal associated with the updated pointer value.

[0027] According to one variation, the reference parameter is a pointervalue for which the associated sample of the reference signal hasmaximum amplitude. According to another variation, the referenceparameter is a set comprising several pointer values. The sample of thereference signal associated with each of the pointer values has amaximum amplitude.

[0028] In general, as will be seen more clearly below, the referenceparameter is chosen as a function of the following. The number ofsamples of the reference signal, the type of increment used to updatethe pointer value, and the shape of the initial analog signal.

[0029] Thus, with the invention, the N least significant bits of asample of the reference signal are stored in the comparison register. Atthe same time, it is verified in a test circuit that the sampleconsidered corresponds to maximum amplitude of the reference signal and,if this is the case, an overflow bit is given. The overflow bit and theN least significant bits of the sample considered are then linkedtogether to obtain the comparison word. The comparison word is thencompared with the number NB given by the counter.

[0030] Thus, when the counter and the comparison register have the samesize, it is possible with the invention to use all the bits of thecounter without its being necessary to use two comparison registers tostore the sample of the reference signal.

[0031] According to one embodiment of the generator, the test circuitcomprises a comparator with two inputs to which the reference parameterand the updated pointer value are applied respectively, and an output isconnected to the overflow register. According to another embodiment, thetest circuit comprises software means to compare the reference parameterwith the updated pointer value.

[0032] The generator described above may be used to control a monophasedevice, for example, of the motor or inverter type. If the device is atriphase device, the invention will preferably use a control circuitcomprising three generators as described above, operating in parallelbut preferably using a single common counter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The invention will be understood more clearly and other featuresand advantages shall appear from the following description of anexemplary implementation of the method and a signal generator accordingto the invention. The description must be read with reference to theappended figures, of which:

[0034]FIGS. 1a to 1 c are graphs of an analog signal, a sampledreference signal and the pulse-width-modulated control signal accordingto the prior art;

[0035]FIG. 2 is a functional diagram of a generator ofpulse-width-modulated signals according to the prior art;

[0036]FIG. 3 is a functional diagram of a generator ofpulse-width-modulated signals according to the present invention; and

[0037]FIG. 4 is an exemplary embodiment of the test circuit illustratedin FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] In all the figures, identical references designate the sameobject. Similarly, the generator according to the invention comprises(FIG. 3), like a known generator, a counter CPC, a reference memory MR,a comparison register RC and a comparator CPT. The generator accordingto the invention also has a pointer PO, a test circuit CTEST and anoverflow register RD.

[0039] The generator is integrated into a microprocessor using N=8 bitregisters and instructions, such as register loading instructionsadapted for use with such registers. The initial analog signal chosenis, in this case, a sine signal, such as the one shown in FIG. 1. Thesignal is sampled on 36 points for a period of the reference signalSREF. Each sampling point I_(i) has an associated number E_(i)representing the amplitude of the initial analog signal at the pointI_(i), with i ranging from 0 to NBECH=35. The reference signal issampled so that the 36 numbers E₀ to E_(NBECH) range from 0 to2^(N)=256. A number E_(i) is equal to zero if the amplitude of thereference signal is minimal (E₂₇ in the example), and a number E_(i) isequal to 256 if the amplitude of the reference signal is maximum (E₉ inthe example).

[0040] The counter CPC is an N=8 bit counter having a clock input toreceive a clock signal CP, and a data output. The counter CPC countspulses of the clock signal CP. At its data output, it gives numbers NBranging from 0 to NBMAX=2⁸−1=255. When it reaches its maximum valueNBMAX, the counter CPC returns to zero, and then continues counting thepulses of the clock signal. The passage to zero of the counter CPC isused as a control signal for the reference memory MR and the pointer PO.

[0041] The pointer PO has a control input connected to the output of theCPC counter, and a data output. The pointer PO gives a number (N=8 bits)ranging from 0 to NBECH, whose value is incremented at each return ofthe counter to zero. NBECH+1 is the number of samples used, which is 36.The pointer PO thus produces numbers I₀=0, I₁=1, etc. Since thereference signal is sampled on 36 points, I₀ corresponds to a phase of0°, I_(i) corresponds to a phase of i*10°, . . . , and I_(NBECH)corresponds to a phase of 350°.

[0042] The reference memory MR comprises a list of NBECH+1 integers E′₀to E′_(NBECH) associated with the numbers I₀ to I_(NBECH) given by thepointer. For all values of i, the number E′_(i) is equal to N leastsignificant bits of the number E_(i). Thus, the most significant bit ofthe numbers E₀ to E_(NBECH) is not stored in the memory MR.

[0043] Since the sampled reference signal SREF represents a sine signal,such as that of FIG. 1a, and since the number of samples chosen is equalto 36, the value E_(i)=256 is attained only for i=9, which correspondsto a 90° phase. In other words, the most significant bit of the numbersE₀ to E_(NBECH) is zero except for that of the number E₉.

[0044] The memory MR has an input command connected to the data outputof the counter CPC, and a data output. When the counter goes to 0 forthe i^(th) time, the memory MR gives the number E′_(i) at its dataoutput. The comparison register RC is an N=8 bit register comprising adata input connected to the data output of the memory MR and to a dataoutput. The comparison register RC successively stores the numbers E₀′to E′_(NBECH), with a number E′i being stored at each return to zero ofthe counter CPC.

[0045] The test circuit CTEST has a data input connected to the outputof the pointer PO, and a data output connected to a data input of theoverflow register RD. The circuit CTEST produces a signal OVF. Theregister RD is a one-bit register. The register RD may also be one bitof an N-bit register identical to the register RC. The circuit CTESTcompares the number I_(i) given by the pointer PO with a predeterminedparameter PARA, which is a number having the same size as the givennumber I_(i).

[0046] If the number given by the pointer PO is equal to the parameterPARA, then the circuit CTEST gives the signal OVF equal to a logic 1.Conversely, if the number I_(i) is different from the number PARA, thenthe circuit CTEST gives the signal OVF equal to a logic 0. The result ofthe comparison is stored in the register RD.

[0047] The number PARA is chosen as a function of the reference signalchosen, and of the pointer PO chosen. The number PARA indicates theindex i for which the number E_(i) is the maximum, equal here to2^(N)=256. Here, the number PARA is equal to 9, because as shown above,the index i=9 corresponds to a 90° phase and a number E₉=256.

[0048] The comparator CPT has two N-bit data inputs respectivelyconnected to the output of the counter CPC, and to the output of thecomparison register RC. The comparator CPT has a one-bit data inputconnected to the output of the overflow register RD, and has a dataoutput at which the pulse-width-modulated control signal SC is given.

[0049] The circuit CPT compares the number NB given by the counter CPCwith an N+1 bit comparison word MC_(i) comprising, in least significantbits, the N bits of the number E′_(i) contained in the comparisonregister RC, and in most significant bits, the contents of the registerRD. The comparison word MC_(i) is equal to the number E_(i) relative tothe sample. If I_(i)≠9, then the value of the contents of the registerRD is equal to zero and the word MC_(i) is equal to “0 E′_(i)”, namelyE_(i). If I_(i)=9, then the value of the contents of the register RD isequal to 1 and the word MC_(i) is equal to “1 E′₉”, namely equal to E₉.

[0050] The circuit CPT finally gives the signal SC=0 if NB≧MC_(i), andSC=1 if NB<MC_(i). The signal SC given by the pulse-width modulatedsignal generator according to the invention is identical to the signalSC produced by a known equivalent generator since the words MC_(i) areidentical to the numbers E₀ to E_(NBECH).

[0051] An exemplary embodiment of the circuit CTEST is shown in FIG. 4.It comprises an adequately sized register RP1 to store the parameterPARA, and a comparator COMP1. The comparator COMP1 has an inputconnected to the data output of the pointer PO, a data input connectedto an output of the register RP1, and a data output connected to theinput of the register RD. The circuit COMP1 compares the number I_(i)given by the pointer PO with the contents of the register RP1, and thecomparison of the result, 0 or 1, is stored in the register RD.

[0052] The general operation of the generator according to the inventionis similar to that of a known prior art generator. Initially, the numberE′₀=128 (in the case of a sine wave such as the one shown here)contained in the memory MR is loaded into the comparison register RC.The pointer PO gives the number I₀=0. The counter CPC is set at 0 andstarts counting the pulses of the clock signal CP.

[0053] Since I₀≠9, a logic 0 is stored in the register RD. Furthermore,the circuit CPT compares the number NB given by the counter CPC with theword MC₀=“0 E′₀” and gives SC=1. Since the inequality NB<MC₀ isverified, the signal SC remains at 1. When the number NB reaches thevalue MC₀, at approximately the half-period of the counter, the signalSC goes to 0. The cyclical ratio of this signal is then equal, for thisperiod of the counter, to about 50%.

[0054] After having reached its maximum value NBMAX=255, the counter CPCreturns to 0 during the next pulse of the clock signal CP. The pointerthen gives the number I₁=1 in this example. Since I₁≠9, the contents ofthe register RD remains unchanged, i.e., equal to 0. Furthermore, thenumber E′₁, equal to about 150, is loaded into the comparison registerRC, and the comparator compares the number NB given by the counter CPCwith the word E₁=“0 E′₁”. It then gives SC=1 so long as NB<0, then SC=0.The cyclical ratio of this signal is then equal, for this period, toabout 59%.

[0055] After having reached its maximum value NBMAX=255, the counter CPCreturns to 0 during the next pulse of the clock signal CP, thencontinues to count. Thus, at each passage to 0 of the counter, thenumbers I₀, I₁, I₂, etc. are successively given by the pointer PO. Atthe same time, the numbers E′₀, E′₁, E′₂, etc. are successively loadedinto the comparison register RC. The comparison in the circuit CPT iscarried out continuously and the signal SC is produced according to thechanges of the numbers Ei (according to the changes in the amplitude ofthe reference signal).

[0056] A time comes when the pointer PO gives the number I₉=9. In thiscase, a logic 1 is stored in the register RD. Furthermore, thecorresponding number E′₉=0 is loaded into the comparison register RC,and the comparator compares the number NB given by the counter CPC withthe word E₁=“1 E′₉” equal to 256. It then gives SC=1 throughout thecycle of the counter since the inequality NB<0 is always verified. Thecyclical ratio of this signal is always equal, for this period, to 100%.Operation of the generator then continues as above.

[0057] With the invention and as in the prior art circuits, the N-bitnumber NB given by the counter is compared with an N+1 bit number. Thisgives a cyclical ratio of 0 to 100% for the signal SC. In the invention,all the bits of the counter CPC will be used. This gives optimumprecision for the size M of this counter CPC. Only one comparisonregister RC having the same size N as the counter CPC is used to storethe reference samples. Only one loading register is therefore necessaryat each passage to zero of the counter to store the samples and preparethe comparison.

[0058] Variations or improvements of the generator according to FIG. 3can easily be planned, alone or in combination with one another. Forexample, the basic elements of the circuit (counter, registers, etc.)are eight-bit elements. It is possible to use differently sizedelements, for example, 12-bit or 16-bit elements.

[0059] The invention is, however, more advantageous when the register RCand the counter CPC used are identically sized. This enables the use ofall the bits of the counter while at the same time using only onecomparison register RC.

[0060] In another variation, the number of samples NBECH may bemodified. In the example described, the number NBECH has been chosen tobe equal to any other value, 1000, 2⁸, 2¹⁶, etc. The choice of thenumber of samples is generally a compromise between the precision of thegenerator. That is, the greater the number of samples, the closer arethe variations of the signal SC to the variations in the amplitude ofthe reference signal, and the more precise is the control of the motor.There may also be a compromise in the computation time which increasesrapidly with the number of samples, and the size of the memory MR (andtherefore that of the total circuit), which too increases with thenumber of samples.

[0061] Of course, the pointer PO must be adapted accordingly. Its sizemust be sufficient to enable the processing of the numbers sized 2⁸, 2¹⁶as the case may be. Similarly, the elements of the circuit CTEST must beadapted accordingly, and especially the parameter PARA must be modified.In the case of an initial analog signal such as that of FIG. 1a and apointer with an increment of 1, the parameter PARA=64 if NBECH=2⁸, andPARA=16384 if NBECH=2¹⁶.

[0062] In yet another variation, the pointer PO may be chosendifferently. In the example described with reference to FIG. 3, thepointer gives numbers incremented by 1: I₀=0, I₁=1, etc. However, it isquite possible to choose another type of increment. For example, it ispossible to use a pointer giving the numbers I₀=0°, I₁=10°, I₂=20°, . .. , I₃₅=350°. It is equally possible to choose a pointer giving I₀=2⁸,I₁=2⁸+2⁸=2*2⁸, I₂=3*2⁸, . . . , I₂₅₅=2⁸*2⁸=2¹⁶. Here too, depending onthe pointer chosen, the circuit CTEST, and especially the parameterPARA, should be adapted accordingly.

[0063] In yet another variation, the initial analog signal used isdifferent from a sine signal. Here too, depending on the initial analogsignal chosen, the parameter PARA would have to be adapted accordingly,as also the circuit CTEST.

[0064] The analog signal may also be a sine signal (such as that of FIG.1a) deformed by the addition of harmonics 3. In this case, the amplitudeof the analog signal is the maximum for two phase values 60° and 120°;and it is the minimum for two phase values 240° and 300°. In this case,the parameter PARA is a set of two values: PARA1=6, and PARA2=12 if thenumber of samples is equal to 36 and if the increment of the pointer isequal to 1. The circuit CTEST is modified to take account of these twovalues, and to test if the number I_(i) given by the pointer is equal toeither of these values. If I_(i) is equal to one of the values of theparameter PARA, then CTEST produces a logic 1, else its produces a logic0.

[0065] The analog signal may also be a square-wave signal or atrapezoidal signal. In this case, the amplitude of the analog signal isthe maximum and constant at least between two phases Phi1 and Ph2. Theparameter PARA then takes a set of values associated with the phasesranging from Ph1 to Ph2. For example, if Ph1=20° and Ph2=200°, thenumber of samples is equal to 36. If the increment of the pointer isequal to 1, then PARA is a set comprising the following numbers: 2, 3,4, . . . , 19, 20. The circuit CTEST is obviously modified to takeaccount of all these values in comparing the number I_(i) with all thesevalues.

[0066] In any case, the parameter PARA, which is a number, or possibly aset of numbers, is chosen as a function of the number of samples NBECH,the type of increment used for the pointer, and the shape of the initialanalog signal.

[0067] In yet another variation, the counter CPC used is different fromthe counter used in the example. The counter can also give numbersdecreasing from its maximum value NBMAX to the value 0, then return toNBMAX and continue to count down. The counter can also give numbersincreasing from 0 to its maximum value NBMAX and then give numbersdecreasing to 0.

[0068] Regardless of the counter chosen, the overall operation of thegenerator is similar. The comparator CPT is adapted to verifying theadequate inequality: NB≧E′i or NB≦E′i or again NB≧E′i only when thenumbers NB change in an upward (or downward) direction, depending on thecounter CPC chosen.

[0069] The generator may also be improved by the addition of means tomodulate the amplitude of the sampled, reference signal SREF used. Withthis improvement, it is possible to produce control signals of variableamplitude. Thus, the power given to the element (motor, pump, etc.)controlled by this signal is modulated.

[0070] The means for the amplitude modulation of the reference signalcomprise an index register RI and a multiplier MULT shown in dashes inFIG. 3. Furthermore, the counter is replaced by an N+N′ bit counter, theregister RC is replaced by an N+N′ bit register, and the circuit CTESTis modified.

[0071] The index register is an N′ bit register in which an amplitudemodulation parameter MA is stored. This parameter MA may be modified bymeans external to the circuit, but remains preferably constantthroughout the period of the sampled reference signal. The number N′ maybe equal to the number N, but not necessarily so.

[0072] The multiplier MULT is a multiplication circuit adapted to themultiplication of the N-bit numbers E₀ to E_(NBECH) to give a result ofN+N′. The N-bit numbers E₀ to E_(NBECH) are stored in the memory MR bythe modulation parameter MA which is stored in the index register RI.The multiplier MULT comprises a data input connected to an N-bit dataoutput of the memory MR, a data input connected to the output of theN-bit register RI, and a data output connected to the data input of thecomparison register RC. The direct link between the memory MR and theregister RC is, in this case, eliminated.

[0073] The circuit CTEST is modified by the addition of a comparatorCOMP2, a register RP2 and a gate OP, shown by the dashed lines in FIG.4. The register RP2 has a size N′ suited to memorizing a predefinedvalue MA0 of the amplitude modulation parameter MA. The value MA0 is,for example, the maximum value that can be taken by the parameter MA.

[0074] The comparator COMP2 comprises an input connected to the dataoutput of the register RI, a data input connected to an output of theregister RP2 and a data output connected to an input of the AND typelogic gate OP, another input of which is connected to the output of thecomparator COMP1. The output of the gate OP is connected to the input ofthe register RD.

[0075] The circuit COMP1 compares the number I_(i) given by the pointerPO with the contents of the register RP, and the result of thecomparison. In parallel, the circuit COMP2 compares the value of theparameter MA with the value MA0 contained in the register RP2. Theresults given by COMP1, COMP2 are combined by the gate OP and the resultof the combination is stored in the register RD.

That which is claimed is:
 1. A method for the generation of apulse-width-modulated signal (SC) out of a reference signal (SREP), inwhich: a counter is incremented, this counter producing numbers NBincremented at each pulse of a clock signal (CP), and a reference number(E′₀ to E′_(ENBECH)) is updated each time the counter (CPC) reaches asetting value (“0”), the reference number (E′₀ to E′_(ENBECH)) relatingto the reference signal (SREF), wherein the following steps are alsoperformed: an overflow bit (OVF) is computed by comparing a pointervalue (I₀ to I_(NBECH)) with a reference parameter (PARA), the pointervalue (I₀ to I_(NBECH)) being updated each time the counter (CPC)reaches the setting value (“0”), and the control signal (SC) is producedby comparing a number NB given by the counter (CPC) with an updatedcomparison word comprising the overflow bit in terms of most significantbits and the updated reference number in terms of least significantbits.
 2. A method according to claim 1, wherein numbers NB and theupdated reference number (E′₀ to E′_(NBECH)) are of the same size N. 3.A method according to one of the claims 1 or 2, wherein the updatedcomparison word (E₀ to E_(NBECH)) is a sample of the reference signal(SREF) associated with the value of the updated pointer.
 4. A methodaccording to one of the claims 1 to 3, wherein the updated referencenumber is obtained by eliminating the most significant bit of the sample(E₀ to E_(NBECH)) of the reference signal (SREF) associated with theupdated pointer value (I₀ to I_(NBECH)).
 5. A method according to one ofthe claims 1 to 3 wherein, to update the reference number (E′₀ toE′_(NBECH)), an updated initial number is multiplied by an amplitudemodulation parameter (MA), said updated initial number being obtained byeliminating the most significant bit of the sample (E₀ to E_(NBECH)) ofthe reference signal (SREF) associated with the updated pointer value.6. A method according to one of the claims 1 to 5, wherein the referenceparameter is a pointer value for which the associated sample (E₀ toE_(NBECH)) of the reference signal (SREF) has a maximum amplitude.
 7. Amethod according to one of the claims 1 to 5, wherein the referenceparameter is a set comprising several pointer values, the sample (E₀ toE_(NBECH)) of the reference signal (SREF) associated with each of saidpointer values having a maximum amplitude.
 8. A generator ofpulse-width-modulated signals to produce a control signal (SC) as afunction of the reference signal (SREF), the generator comprising: acounter (CPC) to count the pulses of the clock signal and give thenumbers NB, and a comparison register to store a reference number (E′₀to E′_(NBECH)) relating to the reference signal (SREF), the referencenumber being updated each time the counter reaches a setting value(“0”), wherein the generator also comprises: a test circuit (CTEST), togive an overflow bit by comparing a reference parameter (PARA) with anupdated pointer value (I₀ to I_(NBECH)) relating to a time baseassociated with the reference signal (SREF), the pointer value (I₀ toI_(NBECH)) being updated each time the counter (CPC) reaches the settingvalue (“0”), an overflow register (RD) to store the overflow bit, and acomparator (CPT) to give the control signal (SC) by comparing a numberNB given by the counter (CPC) with an updated comparison word comprisingthe overflow bit in terms of most significant bits and the updatedreference number in terms of least significant bits.
 9. A generatoraccording to claim 8, wherein the comparison register (RC) and thecounter have the same size N.
 10. A generator according to one of theclaims 8 to 9, wherein the test circuit (CTEST) comprises a comparator(COMP1) with two inputs to which the reference parameter (PARA) and theupdated pointer value are applied respectively, and an output connectedto the overflow register.
 11. A generator according to one of the claims8 to 9, wherein the test circuit (CTEST) comprises software means tocompare the reference parameter (PARA) with the updated pointer value.12. A generator according to one of the claims 8 to 11, also comprisinga reference memory (MR), to store the reference numbers (E′₀ toE′_(NBECH)), said memory comprising a control input connected to anoutput of the counter.
 13. A generator according to claim 12, wherein adata output of the data memory (MR) is connected to a data input of thecomparison register (RC).
 14. A generator according to one of the claims8 to 13, also comprising: an index register (RI) storing an amplitudemodulation parameter (MA), and a multiplication circuit comprising aninput connected to an output of the index register (RI), an inputconnected to the data output of the reference memory (MR), and an outputconnected to the data input of the comparison register.
 15. A monophasedevice, for example of the motor or inverter type, electricallycontrolled by a control circuit comprising a generator according to oneof the claims 8 to
 14. 16. A triphase device, for example of the motoror inverter type, electrically controlled by a control circuitcomprising three generators according to one of the claims 8 to 14, thethree generators working in parallel and using a single counter (CPC).